Computing System - コンピュータアーキテクチャ - (CPU、命令メモリー、データメモリー)

コンピュータシステムの理論と実装
原書

開発環境

• OS X El Capitan - Apple (OS)
• Emacs(Text Editor)
• Java (実行環境)

コンピュータシステムの理論と実装 (Noam Nisan (著)、Shimon Schocken (著)、斎藤 康毅(翻訳)、オライリージャパン)の5章(コンピュータアーキテクチャ)、5.5(プロジェクト)を取り組んでみる。

5.5(プロジェクト)

コード(Emacs)

Memory.hdl

CHIP Memory {
    IN in[16], load, address[15];
    OUT out[16];

    PARTS:
    DMux4Way(in=load, sel[0]=address[13], sel[1]=address[14],
    a=ram0, b=ram1, c=screen);    
    Or(a=ram0, b=ram1, out=ram);
    
    RAM16K(in=in, address=address[0..13], load=ram, out=outram);
    Screen(in=in, load=screen, address=address[0..12], out=outscreen);
    Keyboard(out=outkey);
    
    Mux4Way16(a=outram, b=outram, c=outscreen, d=outkey,
    sel[0]=address[13], sel[1]=address[14], out=out);
}

CPU.hdl

CHIP CPU {

    IN  inM[16],         // M value input  (M = contents of RAM[A])
        instruction[16], // Instruction for execution
        reset;           // Signals whether to re-start the current
                         // program (reset==1) or continue executing
                         // the current program (reset==0).

    OUT outM[16],        // M value output
        writeM,          // Write to M? 
        addressM[15],    // Address in data memory (of M)
        pc[15];          // address of next instruction

    PARTS:
    Mux16(a=instruction, b=outalu, sel=instruction[15], out=outmux);
    
    Not(in=instruction[15], out=nota);    
    Or(a=nota, b=instruction[5], out=outor);
    
    ARegister(in=outmux, load=outor, out[0..14]=addressM, out=outa);
    
    Mux16(a=outa, b=inM, sel=instruction[12], out=outam);

    And(a=instruction[4], b=instruction[15], out=outand);
    DRegister(in=outalu, load=outand, out=outd);

    ALU(x=outd, y=outam, zx=instruction[11], nx=instruction[10],
    zy=instruction[9], ny=instruction[8], f=instruction[7], no=instruction[6],
    out=outM ,out=outalu, zr=zr0, ng=ng0);

    And(a=instruction[15], b=instruction[3], out=writeM);

    And(a=instruction[2], b=ng0, out=out0);
    And(a=instruction[1], b=zr0, out=out1);
    Not(in=ng0, out=notng);
    Not(in=zr0, out=notzr);
    And(a=notng, b=notzr, out=out2);
    And(a=instruction[0], b=out2, out=out3);
    
    Or(a=out0, b=out1, out=out4);
    Or(a=out4, b=out3, out=out5);
    
    And(a=instruction[15], b=out5, out=load0);
    Not(in=load0, out=inc0);
    
    PC(in=outa, load=load0, inc=inc0, reset=reset, out[0..14]=pc);    
}

Computer.hdl

CHIP Computer {

    IN reset;

    PARTS:
    ROM32K(address=pc, out=instruction);
    CPU(inM=inM, instruction=instruction, reset=reset, outM=outM, writeM=writeM,
    addressM=addressM, pc=pc);
    Memory(in=outM, load=writeM, address=addressM, out=inM);
}